1. Field of the Invention
The present invention relates to a counter circuit of digital transmission circuits and more particularly to a technique for reducing noise at the time of operation.
2. Description of the Background Art
FIG. 21 is a circuit diagram of a conventional counter circuit structure. In FIG. 21 three stages of D-type flip-flops FF1 to FF3 which receive a clock CLK in common at their C (clock) inputs, are connected in series. The D-type flip-flop FF1 receives a signal S1 at its D input and outputs a signal S2 from its Q output, the D-type flip-flop FF2 receives the signal S2 at its D input and outputs a signal S3 from its Q output, and the D-type flip-flop FF3 receives the signal S3 at its D input and outputs a signal S4 from its Q output.
NOR gate G10 for three inputs receives signals S2 to S4 and performs NOR operation on the signals S2 to S4, to output a signal S1.
FIG. 22 is a timing chart showing the operation of the counter circuit of FIG. 21. D-type flip-flops FF1 to FF3 latch signals given to their respective D inputs by using the rising edge of a clock CLK as a trigger. Therefore, every clock cycle Tc, the content latched by a D-type flip-flop is transported to the following D-type flip-flop.
When signals S2 to S4 are all "L", a signal S1 becomes "H" by the NOR gate G10. As shown in FIG. 22, the signal of "H" cycles every clock cycle Tc in the order of signals S1, S2, S3, S4, S1 . . . , so that each of the signals S1 to S4 becomes "H" once every four times of the clock cycle Tc of a clock CLK.
Accordingly, the pulse number of a clock CLK, i.e., 4N, is countable by counting the number "N" of how frequently any one of signals S1 to S4 becomes "H". Since the pulse number "4" is countable at a time, the counter circuit with the structure of FIG. 21 is referred to as "4-bit counter circuit."
Unfortunately, when on the above counter circuit the "H" of a signal S2 is transported to a signal S3 between the D-type flip-flops FF1 and FF2, there exists a momentary period that both of the signals S2 and S3 become "L" between the flip-flops FF2 and FF3. Thus, when the "H" of the signal S2 is transported to the signal S3, there exists a momentary period that the signals S2 to S4 are all "L", and hence a spike shaped noise NZ occurs in a signal S1. The same is true for the moment that the "H" of a signal S3 is transported to a signal S4.
As stated above, in the conventional counter circuit there is the danger that the counter circuit will cause a malfunction due to the noise generated in the signal S1.